Parasitic bipolar transistors in NMOS devices are commonly used for protecting integrated circuit pins from ESD damage. The bipolar transistors turn on when current is injected into the base to forward-bias the base/emitter junction. Several trigger devices can be used for injecting the base current. They include resistors, diode strings, and grounded-gate transistors. A normally-on native NMOS device with threshold voltage close to zero was proposed recently as a trigger device in M. D. Ker and K. C. Hsu, “Native-NMOS-triggered SCR (NANSCR) for ESD protection in 0.13-um CMOS integrated circuits”, International Reliability Physics Symposium, Page 381, 2004.
However, if resistors are used for the trigger, large leakage will occur during normal operation. And diode strings are also prone to leakage due to the Darlington effect. While grounded-gate transistors have low leakage, the trigger voltage is high because of the high junction breakdown voltage required to deliver the base current to the parasitic bipolar transistor. Typical 3.3V I/O transistors have a junction breakdown voltage of 7.5V. And the native NMOS transistor has high leakage and can only be shut off if a negative bias is applied to its gate. This requires an on-chip negative-voltage generator to deliver the negative bias.
In the case of a core NMOS transistor with grounded gate and substrate, the junction breakdown voltage is so close to the oxide breakdown voltage that the oxide cannot be protected reliably. For example, in 90 nm technology the junction breakdown voltage is about 4.2 Volts, very close to the oxide breakdown voltage of 4.5 Volts.
If the foregoing NMOS transistors are used to discharge ESD, the trigger voltage is high, and the ESD current is not uniform. This is due to the junction breakdown voltage required for generating substrate current to bias the base of each parasitic bipolar transistor. It is highly desirable to turn on the parasitic bipolar transistors below the junction breakdown voltage; but this requires external currents to be injected to the bases of the NMOS ESD devices. While this method has been used as described in C. H. Lai, et al., “Substrate Pump Circuit and Method for I/O ESD Protection”, U.S. Pat. No. 6,661,273, Dec. 9, 2003, it requires a complicated switching circuit to control ESD discharge and normal operation. In addition, this method uses PMOS current to pump the substrate to the ESD device, and PMOS is known to be slower than NMOS.